1. Field of the Invention
This invention relates generally to integrated circuit fabrication and, more particularly, to masking techniques.
2. Description of the Related Art
As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency in modern electronics, integrated circuits are continuously being reduced in size. To facilitate this size reduction, the sizes of the constituent features, such as electrical devices and interconnect line widths, that form the integrated circuits are also constantly being decreased.
The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. In its most general form, a memory cell typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and read by sensing charge on the storage electrode from the reference electrode side. By decreasing the sizes of constituent electrical devices and the conducting lines that access them, the sizes of the memory devices incorporating these features can be decreased. Additionally, storage capacities can be increased by fitting more memory cells into the memory devices.
The continual reduction in feature sizes places ever greater demands on techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines, on a substrate. The concept of pitch can be used to describe the size of these features. Pitch is defined as the distance between an identical point in two neighboring features. These features are typically defined by spaces between adjacent features, which are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space separating that feature from a neighboring feature. Due to factors such as optics and light or radiation wavelength, however, photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
“Pitch doubling” is one method proposed for extending the capabilities of photolithographic techniques beyond their minimum pitch. Such a method is illustrated in FIGS. 1A-1F and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, photolithography is first used to form a pattern of lines 10 in a photoresist layer overlying a layer 20 of an expendable material and a substrate 30. As shown in FIG. 1B, the pattern is then transferred by an etch step (preferably anisotropic) to the layer 20, forming placeholders, or mandrels, 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of material is subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40 by preferentially etching the spacer material from horizontal surfaces in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 are then removed, leaving behind the freestanding spacers 60, which together act as an etch mask for patterning underlying layers, as shown in FIG. 1F. Thus, where a given pitch formerly included a pattern defining one feature and one space, the same width now includes two features and two spaces defined by the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased.
It will be appreciated that while the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” That is, conventionally “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein.
The critical dimension of a mask scheme or circuit design is the scheme's minimum feature dimension. Due to factors such as geometric complexity and different requirements for critical dimensions in different parts of an integrated circuit, typically not all features of the integrated circuit will be pitch multiplied. Consequently, pitch multiplied features will often need to be connected to or otherwise aligned with respect to non-pitch multiplied features in some part of the integrated circuit. Because these non-pitch multiplied features generally have larger critical dimensions than the pitch multiplied features, the margin of error for aligning the non-pitch multiplied features to contact the pitch multiplied features can be small. Moreover, because the critical dimensions of pitch-multiplied lines may be near the resolution and/or overlay limits of many photolithographic techniques, shorting neighboring pitch multiplied features is an ever-present possibility. Such shorts can undesirably cause the integrated circuit to malfunction.
Accordingly, there is a need for methods which allow increased margins of error for forming contacts between features of different sizes, especially for forming contacts between pitch multiplied and non-pitch multiplied features.